Method for driving display panel

ABSTRACT

A method for driving a display panel, in which a false gaseous discharge of a display cell is prevented via an initialization sequence containing a reset pulse and an initialization pulse. Stable initialization is achieved by applying the initialization pulse to the common electrode after the reset pulse. The initialization pulse rises up in one step. Alternatively, the initialization pulse is a complex pulse having second-step pulse that rises up within 1 μs after the rise of its first-step pulse. A stabilization sequence can be inserted between the initialization sequence and a discharge maintenance sequence.

TECHNICAL FIELD

The present invention relates to a method for driving a discharge panelthat provides a display by gaseous discharge.

More particularly, the invention pertains to a method for driving adisplay panel of the type wherein a common electrode and a discreteelectrode are connected to each of plural display cells arranged in amatrix form, a display pulse for display operation is applied to thecommon electrode and a control voltage for controlling a discharge ateach display cell is applied to the discrete electrode to controlgaseous discharge at each display cell to thereby provide an imagedisplay.

BACKGROUND ART

There has been known so far a panel that produces a display bycontrolling a gaseous discharge for each display cell, such as a plasmadisplay panel. For normal discharge in such a display panel it isnecessary that charges stored be always held in a state suitable fordischarge. To this end, it is customary in the art to regularlyinitialize all the display cells as by removing stored charges thattrigger an unintended discharge.

Such initialization schemes are described, for example, inJP-A-10-143106, JP-A-8-278766, JP-A-7-140927, JP-A-9-325736 andJP-A-8-212930.

While various initialization schemes have thus been proposed, it isrequired to perform initialization that matches each particulardischarge stricture, discharge condition and panel driving method.

The inventor of the present invention has filed a patent application onan initialization sequence including a negative reset pulse (JapanesePat. Appln. Hei 10-276735 filed Sep. 30, 1998; U.S. application Ser. No.09/261,260 filed Mar. 3, 1999). This case is an improvement on hisprevious invention.

A description will be given first of the invention described in theabove patent application.

FIG. 16 is a diagram schematically depicting a gaseous discharge displaypanel and its drive circuit in their entirety.

The panel has 640 by 480 pixels arranged in a matrix form. Unit panels11, 12, . . . 140, 21, 22, . . . 240, . . . , 301, 302, . . . 3040, eachconsisting of 16 by 16 pixels, are arranged with 40 rows and 30 columnsto form the panel in its entirety.

Each electrode is connected to a common electrode and a discreteelectrode. By controlling the voltage of the discrete electrode whileapplying display pulses to the common electrode, discharge at each pixelis controlled to thereby perform ON/OFF control of display.

And 640 by 480 pieces of data necessary for controlling the voltages ofthe discrete electrodes of the entire panel are input as data of oneframe to a video interface circuit 100.

The data of one frame is provided from the video interface circuit 100to the unit panels via 30 bus circuits 101, 102, . . . , 130.

The first bus circuit 101 extracts 640 by 16 pieces of data from the 640by 480 pieces of data, and sends them to the 40 unit panels 11, 12, . .. , 140. Based on addresses assigned to the data, the unit panels 11,12, . . . , 40 each receive 16 by 16 pieces of data.

In the unit panels 11, 12, . . . , 140 one piece of data is allocated toeach pixel by a drive shift register to control the voltage of thediscrete electrode. Each piece of data consists of 24 bits. They areeight bits for R (red), eight bits for G (green) and eight bits for B(blue). The 8-bit data is used to control the brightness of display in256 steps.

The other bus circuits 102, . . . , 130 also respectively extract 640 by16 pieces of data and send them to the unit panels 21, 22, . . . , 240,. . . , 301, 302, . . . ,3040. And the unit panels 21, 22, 240, 301,302, . . . , 3040 each receive 16 by 16 pieces of data and controlvoltages of discrete electrodes of the 16 by 16 pixels.

The 640 by 480 pieces of data of one frame are input as data of oneframe during pulse intervals of a vertical sync signal V. sync shown inFIG. 17( a). A horizontal sync signal H. sync shown in FIG. 17( b) isgenerated 480 times per frame. A single horizontal sync signal H. syncis followed by 640 pieces of data being input.

In this display panel each display cell is connected to the commonelectrode and the discrete electrode; the discrete electrode is drivenfor each display cell and the common electrode is driven in common toplural cells. And display pulses are applied to the common electrode andthe application of a positive control voltage by the discrete electrodeis controlled for each cell, by which a discharge is controlled for eachdisplay cell to provide a display. The display pulse of the commonelectrode and the control voltage of the discrete electrode are producedfor each unit panel and provided to each display cell.

FIG. 18 depicts the common electrode-applied display pulse, the discreteelectrode control voltage and discharge waveform for each frame. FIG. 18shows the case of a stable discharge. Each frame starts with aninitialization sequence, followed by display sequences.

In the duration of one display pulse the discharge is generated twice.The first discharge is a storage discharge and the second an erasingdischarge. Positive rise-up of the discrete electrode control voltagestops the discharge. The rise-up timing of the discrete electrodecontrol voltage is controlled by the 8-bit data in 256 steps.Accordingly, the brightness of display is also controlled in 256 steps.When the positive rise-up timing of the discrete electrode controlvoltage is brought forward, the frequency of occurrence of the dischargedecreases, reducing the brightness of display.

FIG. 19 is a diagram showing the relationship between the voltage of thecommon electrode and the discharge in the initialization sequencedepicted in FIG. 18. The left-hand side is the common electrode and theright-hand side the discrete electrode.

The display pulse is formed by a two-step voltage, which increases anddecreases in stages; the absolute value of the voltage of a reset pulsemay preferably be set above the first-stage voltage value of the displaypulse. With such a display pulse, it is possible to cause twodischarges, i.e. a charge storage discharge and a stored charge removaldischarge, by one shot of the display pulse. Then, when a stabledischarge takes place, no reset pulse needs to be inserted.

Incidentally, it is preferable to apply the reset pulse once for each orplural frames. This provides frames free from the necessity of insertingreset pulses, imparting flexibility to the processing involved.

Potentials and charges of the both electrodes at times (1) through (6)are described below. The left-hand side is the common electrode and theright-hand side the discrete electrode.

At time (1) the voltages of the both electrodes are 0 V, and nodischarge occurs. At time (2) the voltage of the common electrodereaches 360 V, causing a discharge. This is the storage discharge.Negative charges resulting from the discharge are attracted to thecommon electrode, whereas positive charges are attracted to the discreteelectrode. At time (3), the effective voltage of the common electrodedrops below 360 V due to the negative charges attracted thereto,stopping the discharge. At time (4), when the voltage of the commonelectrode is reduced down to 0 V, a discharge is caused by the potentialdifference between the both electrodes due to the charges attracted tothem. This is removal discharge. At time (5) the discharge stops and thestored charges also disappear. At time (6) a reset pulse of −180 V isapplied to the common electrode, but no change occurs since no storedcharges exist in this case.

The common electrode in this display panel is driven using a complexdisplay pulse whose voltage changes in two stages. And the chargestorage discharge and the stored charge removal discharge are carriedout by a single shot of this complex display pulse. Accordingly, it ispossible, theoretically, that charges are automatically removed even ifthe display discharge is repeated. In practice, however, charges arestored and remain unremoved due to insufficient voltage application andthe repetition of charge and discharge operations, resulting in thedisplay becoming unstable.

As a solution to this problem, it is conventional to initialize thedischarge cell condition through the inversion of charges at the displaycell by applying a positive pulse to every discrete electrode once perframe or frames, or applying a negative pulse (a reset pulse) duringintervals between successive applications of display pulses to thecommon electrode. The application of one complex display pulse and onereset pulse is referred to as an initialization sequence.

FIGS. 20 and 21 are diagrams showing how charges stored by an unstabledischarge are removed by the reset pulse.

FIG. 20 shows the display pulse to the common electrode and the discreteelectrode control voltage and the discharge waveforms in one frame. Whatare depicted in FIG. 20 are the same as those in FIG. 18 except that adischarge is caused by the reset pulse of the initialization sequence.

FIG. 21 shows the relationship between the voltage and discharge at thecommon electrode in the initialization sequence depicted in FIG. 20. Theoperations at times (1) through (4) are the same as in FIG. 19. At time(5) negative charges are stored on the common electrode due to anunstable discharge. Even if the display pulse of 360 V is applied to thecommon electrode in the next cycle (2) while leaving the negativecharges unremoved, the effective voltage of the common electrode doesnot reach 360 V, and a discharge is hard to occur. Then, at time (6) thereset pulse of −160 V is applied to the common electrode to dischargethe stored charges. At time (7) after the discharge positive charges areattracted to the common electrode, and negative charges are attracted tothe discrete electrode. Since the positive charges are stored on thecommon electrode, its discharge will not be hindered by the storedcharges when the display pulse is applied to the common electrode in thenext display cycle (2). In this instance, since the stored charges onthe common electrode are positive, the application of the display pulseraises its effective voltage above the applied voltage, facilitating thedischarge. This gives rise to another problem. The display pulse isapplied at 160 to 180 V in the first stage and 320 to 360 V in thesecond stage; however, facilitating the discharge by the stored chargesleads to the occurrence of a false discharge in the first stage.

In controlling the entire display panel, characteristic variations arecaused in the panel according to its manufacturing conditions, and onlywith the above-mentioned discharge stabilization scheme, it isimpossible to provide a sufficient voltage width (margin) for control,giving rise to the problem of false discharge. Further, characteristicvariations are also present for each panel; to solve these problems, itis necessary to maintain stable discharge and provide a sufficientmargin.

Moreover, the initialization sequence is effective for a cell in anunstable state, but it means a voltage change ineffective for stabledischarge, sometimes making the stable discharge unstable. Accordingly,it is necessary that the initialization sequence be adapted not toaffect the stable cell.

Additionally, data to be provided to the discrete electrode forindividual control of each cell is usually transferred from a logiccircuit, and a high voltage driver IC is used to control the cell. Atthis time, high-voltage switching on the part of the common electrodecauses noise in no small way, which affects the data by the logiccircuit, leading to a false display. Accordingly, it is necessary toreduce noise in the sequence for the common electrode and the transferof data for each cell.

DISCLOSURE OF THE INVENTION

An object of the present invention is to prevent a false discharge thatis caused by the reset pulse of the initialization sequence.

Another object of the present invention is to maintain stable dischargeby providing a sufficient voltage margin of the display pulse, therebypreventing a false discharge resulting from characteristic variationsfor each panel.

Another object of the present invention is to prevent a stable cell frombeing affected by the initialization sequence.

Still another object of the present invention is to reduce noise that iscaused in the data to be sent to the discrete electrode by thehigh-voltage switching on the part of the common electrode.

The display panel driving method according to an aspect of the presentinvention is a method for driving a display panel wherein a commonelectrode and a discrete electrode are connected to each of pluraldisplay cells arranged in a matrix form, an initialization sequencevoltage is applied to the common electrode, then a display pulse fordisplay operation is applied to the common electrode, and a controlvoltage for controlling the discharge period in each display cell isapplied to discrete electrode, thereby controlling the gaseous dischargein each display cell; the above-mentioned initialization sequencecomprises the following steps (a) and (b).

-   -   (a) Step of supplying the common electrode with a reset pulse        opposite in polarity to the display pulse for the inversion of        charges stored on the said electrode.    -   (b) Step of supplying the common electrode with a single-step        pulse of the same polarity as that of the display pulse to the        common electrode.

Since the pulse in step (b) of the initialization sequence is asingle-step, no false discharge results from the inversion of thecharges in step (a).

The display panel driving method according to another aspect of thepresent invention is a method that uses, in place of the single-steppulse in said step (b), a dual-step pulse whose second-step pulse risesup within 1 μs after the rise-up of first-step pulse.

Since the pulse in step (b) of the initialization sequence rises in thesecond step within 1 μs after the first-step rise, no false dischargeresults from the inversion of the charges in step (a).

The display panel driving method according to another aspect of thepresent invention is a method for driving a display panel wherein acommon electrode and a discrete electrode are connected to each ofplural display cells arranged in a matrix form, an initializationsequence voltage is applied to the common electrode, then a displaypulse for display operation is applied to the common electrode, and acontrol voltage for controlling the discharge period in each displaycell is applied to discrete electrode, thereby controlling the gaseousdischarge in each display cell; in this method, the period in which datafor controlling the discharge period of each display cell is transferredto a drive circuit of the discrete electrode is set in the period duringwhich no voltage is applied to the common electrode.

Since the data transfer is carried out while no voltage is applied tothe common electrode, it is possible to prevent noise from being causedin the data transferred.

The display panel driving method according to another aspect of thepresent invention is a method for driving, by the following sequences(a), (b) and (c), a display panel wherein a common electrode and adiscrete electrode are connected to each of plural display cellsarranged in a matrix form.

-   -   (a) Initialization sequence for applying an initialization        voltage to the common electrode.    -   (b) Stabilization sequence for applying a display pulse for        display operation to the common electrode to perform a gaseous        discharge of each display cell.    -   (c) Maintenance sequence for controlling the gaseous discharge        period of each display cell by controlling the period in which        to apply a display pulse for display operation to the common        electrode and a discharge suppression pulse to the discrete        electrode.

Since the stabilization sequence is provided between the initializationsequence and the maintenance sequence, each cell state stabilizes,preventing its false discharge.

The display panel driving method according to still another aspect ofthe present invention is a method in which the period in which not toapply voltages to both of the common electrode and the discreteelectrode is set between the sequences (a) and (b), or between thesequences (b) and (c), or in place of the sequence (b).

The false discharge can be prevented by setting a stabilization periodin which no voltages are applied to the common electrode and thediscrete electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the electrode structure of one display cell.

FIG. 2 is a diagram depicting an array of display cells that are drivenby the display panel driving method of the present invention.

FIG. 3 is a diagram showing the connection between the electrode of onedisplay cell and its drive circuit.

FIG. 4 is a connection diagram of a circuit for driving the commonelectrode in the display panel driving method of the present invention.

FIG. 5 is a waveform diagram showing an initialization sequenceaccording to an embodiment of the display panel driving method of thepresent invention.

FIG. 6 is a waveform diagram showing the initialization sequence used ina conventional driving method.

FIG. 7 is a waveform diagram showing an initialization sequence usingtwo initialization pulses in succession in the display panel drivingmethod of the present invention.

FIG. 8 is a waveform diagram showing an initialization sequence using areset pulse of a less-than-5-μs duration in the display panel drivingmethod of the present invention.

FIG. 9 is a waveform diagram showing a basic initialization sequence foruse in the display panel driving method of the present invention.

FIG. 10 is a waveform diagram showing the applied voltage of the commonelectrode, the period of control data transfer to the discreteelectrode, and the voltage waveform of the discrete electrode in anotherembodiment of the display panel driving method according to the presentinvention.

FIG. 11 is a waveform diagram showing the voltage waveform of the commonelectrode, the period of control data transfer to the discreteelectrode, and the voltage waveform of the discrete electrode.

FIG. 12 is a diagram showing the relationship between the pulse intervalfrom the fall of the common electrode voltage to the rise-up of asuppression pulse to be applied to the discrete electrode and a marginvoltage.

FIG. 13 is a waveform diagram showing the display panel driving methodof the present invention which involves a stabilization sequence.

FIG. 14 is a diagram showing the relationship between the number ofstabilization pulses and the frequency of occurrence of false dischargein the stabilization sequence in FIG. 13.

FIG. 15 is a waveform diagram showing the display panel driving methodof the present invention in which a stabilization period is provided.

FIG. 16 is a diagram depicting the arrangement of the display panel andthe transfer routes of control data to discrete electrodes.

FIG. 17 is a diagram showing vertical and horizontal sync signals fordriving the display panel and the transfer of control data to thediscrete electrodes.

FIG. 18 is a diagram showing a display pulse applied to the commonelectrode, the discrete electrode control voltage and a dischargewaveform in the case of a normal discharge in the invention described inthe inventor's prior application.

FIG. 19 is a diagram showing variations in the voltage waveform of thecommon electrode and variations of charges on the common electrode andthe discrete electrode in the case of FIG. 18.

FIG. 20 is a diagram showing a display pulse applied to the commonelectrode, the discrete electrode control voltage and the dischargewaveform in the case of an unstable discharge in the invention describedin the inventor's prior application.

FIG. 21 is a diagram showing variations in the voltage waveform of thecommon electrode and variations of charges on the common electrode andthe discrete electrode in the case of FIG. 20.

BEST MODE FOR CARRYING OUT THE INVENTION

Next, a description will be given, with reference to the accompanyingdrawings, of the display panel driving method according to the presentinvention.

Embodiment 1

FIG. 1 is a diagram depicting one display cell (one color) in thedisplay panel that embodies the present invention. The display panel hasits back covered with a back glass board 10. A recess 12 made in theback glass board 10 is coated all over its interior surface with afluorescent layer 14. On the back of a front glass board 20 (on the sidefacing the back glass board 10) there are disposed a pair of transparentelectrodes 24 a and 24 b. A dielectric layer 26 is formed covering them,and is coated with a protective film 28. Accordingly, the protectivefilm 28 usually formed of MgO faces the recess 12. And, by applying apositive display pulse to the common electrode and holding the discreteelectrode at a sufficiently low voltage (for example, 0 V), a dischargeis caused in a portion of the recess 12 adjacent the protective film.Applying a positive voltage to the discrete electrode, the voltage valuebetween the discrete electrode and the common electrode reduces,stopping the discharge.

FIG. 2 illustrates in block form the configuration of a unit displaypanel, and FIG. 3 shows in block form the connections of discharge cellsand their drive circuits.

The unit display panel comprises cells arranged in the form of a n by mmatrix. In this embodiment n=m=16. One display cell consists of red (R),green (G) and blue (B). Each display cell has a common electrode anddiscrete electrode. The common electrode of every cell is supplied witha common electrode drive pulse. Applied to the common electrode are GND,160 V, 320 V and negative voltages. The discrete electrode of eachdisplay cell is supplied with a different discrete electrode drivepulse. Upon application of a 160-V pulse to the discrete electrode, thedischarge stops.

FIG. 4 shows a common electrode drive circuit. A 160-V power supply Vsis grounded via transistors Q1 and Q2. The transistors Q1 and Q2 havetheir gates connected to a first control part 30, and the transistors Q1and Q2 are turned ON and OFF by control signals from the first controlpart 30. By turning ON the transistor Q1 and OFF the transistor Q2, thevoltage V_(s) is output from the node (a V_(s) output point)intermediate between the transistors Q1 and Q2 to the next stage. Thecircuit by the transistors Q1 and Q2 is a circuit on the part of thepower supply, which is formed on a circuit board different from that onwhich there are formed the following circuits indicated by the brokenlines in FIG. 4, and it has a ground potential different from that ofthe latter.

Connected to the intermediate node of the transistors Q1 and Q2 is acapacitor C1 grounded at the other end. Further, connected to the V_(s)output point are transistors Q3 and Q4 grounded at one end. Thetransistors Q3 and Q4 have their gates connected to a second controlcircuit 32, and the ON-OFF operation of the transistors Q3 and Q4 iscontrolled by the second control circuit 32. Moreover, transistors Q5and Q6 grounded at one end are connected to the V_(s) output point via adiode D1. The transistors Q5 and Q6 have heir gates connected to a thirdcontrol circuit 34, and the ON-OFF operation of the transistors Q5 andQ6 is controlled by the third control circuit 34. The transistors Q3,Q4, Q5 and Q6 are turned ON and OFF with the transistor Q1 held ON andthe transistor Q2 OFF, as described below. As a result, he commonelectrode is supplied with such a two-step display pulse as depicted inFIG. 19. By bringing the rise-up time of the second-step pulse close tothe rise-up time of the first-step pulse, a virtually one-step pulse isproduced. The limit on the interval between the rise-up times of theboth pulses depends on the transistor switching time.

TABLE 1 Q3 Q4 Q5 Q6 (1) AT the time of 0 V OFF ON OFF ON (2) At the timeof 1st-step OFF ON OFF OFF pulse rise-up (3) OFF ON ON OFF (4) At thetime of 2nd-step OFF OFF ON OFF pulse rise-up (5) ON OFF ON OFF (6) Atthe time of 2nd-step OFF OFF ON ON pulse falling (7) OFF ON ON OFF (8)At the time of 1st-step OFF ON OFF OFF pulse falling (9) OFF ON OFF ON

That is, the potential of the common electrode is reduced down to theground potential (0 V) by turning OFF the transistor Q5 and Q6 ON, andthe potential of the common electrode is raised to Vs by turning ON thetransistor Q5 and OFF Q6. At this time, the transistor Q4 is held ON, bywhich charges equivalent to V_(s) are stored in a capacitor C2. And, byturning OFF the transistor Q4 and ON Q3, the capacitor C2 is made tohave the potential V_(s) at its end connected to the transistor Q3.Since the capacitor C2 is charged corresponding to V_(s), the voltage ofthe common electrode becomes 2V_(s). In this way, a second-step voltage2 V_(s) can be generated. And, by turning OFF the transistor Q3 and ONQ4, the voltage of the common electrode returns to V_(s), and by turningOFF the transistor Q5 and ON Q6, the voltage of the common electrodereturns to the power-supply voltage 0; thus, the two-step display pulsecan be created.

Next, the transistor Q1 is turned OFF and Q2 ON with the transistor Q5held OFF and Q6 ON. As a result, the upper potential of the capacitor C1is fixed at the ground potential 0 V at its the power supply side. Onthe other hand, the lower-side ground potential of the capacitor C1 isthe ground potential of this drive circuit, and is not always 0 V. Then,this ground potential becomes −V_(s), and the potential of the commonelectrode grounded via the transistor Q6 becomes −V_(s). Hence, thereset pulse shown in FIG. 19 is applied to the common electrode.

The reset pulse is opposite in polarity to the display pulse, and itsmagnitude is V_(s) that is the same as that of the first-step pulse.This V_(s) is, for example, 160 V (in the range of 150 V to 200 V), atwhich a discharge is caused when wall charges remain. Accordingly, theapplication of the reset pulse causes a discharge when the wall chargesremain unremoved, and as a result, the wall charges are removed.

The relationship between the voltage application to the common electrodeand the discrete electrode and the discharge is the same as describedabove with reference to FIGS. 18 to 21, except common electrode pulsefollowing the reset pulse becomes one step. FIGS. 18 and 19 show thestate of normal discharge, and FIGS. 20 and 21 the state of unstabledischarge when wall charges remain unremoved. As described above, whenan unstable discharge takes place and wall charges remain unremoved, theapplication of the reset pulses causes a discharge, removing the wallcharges.

In this case, the erase pulse may preferably be of the order of thefirst-step voltage of the display pulse, and when wall charges persist,the application of this pulse ensures the charge removal discharge.Further, the generation of the reset pulse of the same voltage as thedisplay pulse permits simplification of the drive circuit.

The reset pulse needs to be of long duration sufficient to ensuredischarge when wall charges persist after the discharge for display. Toensure the discharge, a duration of about 5 μsec is required in thisembodiment. This is influenced by the size of the display cell, forinstance. The time of this discharge is the same as that of thedischarge by the display pulse, and it is preferable to insert the resetpulse of about 5 μsec duration 15 μsec after or so after the fall of thedisplay pulse to 0 (GND). Since the discharge time changes with the sizeof the display cell, the above-mentioned times 15 μsec and 5μsec bothchange. Then, the time interval from end of the display pulse to thestart of the reset pulse and the duration of the reset pulse maypreferably be set to a 3:1 ratio or so. Incidentally, this relationshipapplies to the case where the both times are each set to the smallestvalue; it does not matter if the both times are chosen sufficientlylong.

The arrangement of the display panel and the data transfer to thediscrete electrode in this embodiment are the same as in FIGS. 16 and17. However, the number of unit panels, each having 16 by 16 pixels,arranged in a matrix form in not limited specifically to 30 in columnand 40 in row.

FIG. 5 shows the initialization sequence, waveforms being depicted incomparison with those in the FIG. 6 prior art example. The waveform ofthe initialization pulse applied to the common electrode in FIG. 5 is awaveform resulting from the simultaneous application of a first voltagepulse and a second voltage pulse superimposed thereon. The dischargelight emission (normal waveform) shown has a discharge waveform whensuch a normal discharge as shown in FIG. 19 is caused. The dischargelight emission (non-controlled waveform) has a discharge waveform whenstored charges are present as depicted in FIG. 21. With such aninitialization sequence as shown in FIG. 5, it is possible to avoid thestate in which when the initialization pulse is applied under unstableconditions, the application of the first voltage pulse causes a falsedischarge at a voltage above the discharge start voltage under theinfluence of residual charges or the like as indicated by thenon-controlled waveform in FIG. 5. In the case of the non-controlledwaveform in the FIG. 6 prior art example, a false discharge occurs atthe leading edge of the first voltage pulse. Further, by causing thefirst and second voltage pulses to fall at one stroke to apply a largepotential difference at one time, it is possible to obtain a largercharge removal discharge than in the case of causing the voltage pulsesto fall separately.

In this display panel, 175 V is applied as the first and second voltagepulses, and the resulting discharge occurs 0.4 μs after the voltageapplication. At present, the voltage rise-up by high voltage switchingtakes 0.3 μs; hence, by applying the second voltage to be superimposedon the first voltage within 0.1 μs after the duration of the firstvoltage pulse, it is possible to obtain a pulse waveform that satisfiesthe above requirement. By the rise-up of the second voltage pulse within1 μs after the rise-up of the first voltage pulse, the false dischargecan be prevented to some extent.

The time width during which the second voltage pulse falls and the firstvoltage pulse is applied is made shorter than 0.1 μs to apply a largevoltage difference at the time of the fall, by which a larger chargeremoval discharge can be implemented, and as a result, stable controlcan be performed.

The initialization sequence shown in FIG. 5 is performed once per frameor frames.

In the initialization sequence in FIG. 5, the reset pulse precedes theinitialization single pulse but the order of the both pulses may bereversed.

Embodiment 2

Further, the positive initialization sequence pulse that is applied tothe common electrode may also be divided into two as depicted in FIG. 7.In the case where a pulse by the sequence of the previous frame is notimmediately followed by the application of the initialization pulse orwhere the discharge is suppressed in the previous frame, the firstdischarge in the next frame may sometimes become unstable. To solve thisproblem, the initialization sequence is used for stable discharge; butthe addition of one more pulse ensures re-charging after the firstdischarge, thereby providing increased stability.

Embodiment 3

Moreover, the width of the reset pulse is reduced as shown in FIG. 8.This prevents that a cell in its stable discharge state is caused by anunnecessary reset pulse to perform a false discharge. Such a falsedischarge is likely to occur in the case of keeping on applying voltageto the display cell. Accordingly, the probability of occurrence of thefalse discharge increases with an increase in the reset pulseapplication period. Further, in the case of initialization by the resetpulse during an unstable discharge shown in FIG. 21, a discharge lightemission occurs 0.3 μs to several μs after the fall of the reset pulse.On this account, setting the rest pulse width to about 5 μs makes itpossible to prevent the stable-state cell from a false discharge whilemaintaining the reset function.

FIG. 9 shows a waveform diagram in the case of Embodiment 1 in which thewidth of the reset pulse is not reduced.

Embodiment 4

FIG. 10 shows driving waveforms including a signal waveform for settingthe output timing of the discrete electrode. Usually, a suppressionpulse to be applied to the discrete electrode (in this case, the appliedvoltage being set to 115 V) is set to rise up during interval betweenvoltage applications to the common electrode. For voltage applicationwith certain timing, it is necessary to set the ON-OFF timing forindividual discrete electrodes of the entire panel, and a data transferperiod for all the electrodes is required. By simultaneously outputtingthe data sent during the transfer period with the voltage applyingtiming, the discrete electrodes of all the cells can be turned ON/OFF atthe same timing. Since this data is usually driven by an element calleda high voltage driver IC, the data transfer is carried out by a logiccircuit. During the voltage application to the common electrode, anappreciable amount of noise is caused by the switching of the highvoltage pulse that is applied to the common electrode. For example, ifthis noise affects the transferred data, it affects the data transferoperation as CLK noise, or H/L of the data itself is reversed and thevoltage application to the discrete electrode is reversed—this givesrise to the problems such as the reversal of light emission andnon-emission, false lighting and non-lighting state.

Accordingly, by setting the data transfer period for the discreteelectrode in the interval between the voltage applications to the commonelectrode, it is possible to eliminate the influence of noise withoutfail.

For example, 4-bit data is transferred at 5 MHz to 192 discreteelectrodes of the panel. In this case, since the data transfer calls forat least

-   -   192/4×1/(5×10⁶)=9.6 μs,        about 10 μs is set as the time width during which no voltage is        applied to the common electrode.

Further, assume that the data output point is set in the period of thefirst voltage pulse of the complex pulse to be applied to the commonelectrode and prior to the superimposition thereon of the second voltagepulse on the first one. In this case, since the first voltage pulse isset below the discharge start voltage, the voltage of the discreteelectrode will not affect the discharge when stable light emissioncontinues.

This provides a margin in the period for sending data for the voltageapplication t the discrete electrode. Further, by lengthening the timeinterval between the immediately previous pulse applied to the commonelectrode and the driving of the discrete electrode, it is possible toprovide a sufficient amount of time for space charges resulting from theremoval discharge having occurred at the fall of the pulse applied tothe common electrode decrease in the cell space. When the space chargeremains in the cell, this charge promotes discharge and hence lowers thedischarge start voltage as an externally applied voltage value,increasing the possibility of false discharge. With the above-mentionedtime interval sufficiently lengthened, it is possible to lessen theinfluence of the space charge, leading to an increase in the marginvoltage.

FIG. 11 shows, for the purpose of comparison, the data output timing ofthe discrete electrode and the voltage waveform applied to the commonelectrode in the prior art.

FIG. 12 shows the relationship between the pulse interval from the fallof the pulse applied to the common electrode to the rise-up of the pulseto be applied to the discrete electrode and the common electrode voltage(margin voltage) that can be controlled. In this display panel, to set asufficient margin voltage that can be controlled without causing falsedischarge, a time width is set 10 μs or more after the fall of the pulseapplied to the common electrode to thereby secure the margin voltage. Inthis case, since the rise-up point of the pulse to be applied to thediscrete electrode is in the first voltage pulse period of the complexpulse to be applied to the common electrode and prior to thesuperimposition thereon of the second voltage pulse, the pulse intervalcan be increased approximately 2 μs or so, as a result, the marginvoltage increases about 2 V.

Embodiment 5

FIG. 13 depicts driving waveforms for the common electrode and thediscrete electrode. A pulse similar to the maintenance pulse is appliedto the common electrode as a stabilization sequence between theinitialization sequence that is inserted once per frame or frames andthe maintenance sequence for maintaining the discharge. It isempirically known that the insertion of the stabilization sequencecauses repetition of a certain discharge emission about the beginning ofthe frame to bring all the cells into their stable state, thuspreventing false discharge. The larger the number of stabilizationpulses, the higher the stability; however, since luminance is determinedby the number of pulses, the insertion of many stabilization pulses ineach frame increases the brightness (luminance level) of a blackdisplay, resulting in impaired contrast of the display image.

FIG. 14 shows the relationship between the number of stabilizationpulses and the number of occurrences of false discharge under a certainunstable condition. The false discharge mentioned herein is alow-frequency (below 1 Hz) visible false discharge that is caused by thelack of a certain amount of wall charge in the cell, and it can be seenthat the occurrence of false discharge could be avoided by increasingthe number of stabilization pulses used. By setting the number ofstabilization pulses to eight in this case, it is possible to achievestabilization and minimize the deterioration of contrast.

Embodiment 6

FIG. 15 shows driving waveforms for the common electrode and thediscrete electrode. As shown, a certain stabilization period is providedbetween the initialization sequence and maintenance sequence for thecommon electrode. In particular, after a single initialization pulse, alarge erasing discharge occurs in every cell, and space charge iscreated in large quantities over the entire panel; accordingly, theamount of space charge remaining increases and it also remains for along time. Hence, the discharge by the immediately subsequent pulsevoltage application is readily affected by the space charge—this leadsto the occurrence of false discharge and the reduction in the margin.Therefore, the influence of space charge could be avoided by setting asufficient time width between the initialization sequence inserted onceper frame or frames and the discharge maintaining pulse.

Further, in the case of using the stabilization sequence described abovein Embodiment 5, it is possible to achieve stabilization by Embodiment 5and avoid the influence of false discharge by similarly setting asufficient time width between the initialization sequence and thestabilization sequence, or between the stabilization sequence and thedischarge maintaining sequence.

In this case, however, too long a stabilization period limits the numberof pulses that can be inserted in the frame, resulting in decreasing themaximum luminance. Hence, the stabilization period needs to be set to anappropriate value according to the display luminance and power of thepanel specifications. In this embodiment the stabilization period is setto about 1 ms for one frame 16.6 ms long.

1. A method for driving a display panel, in which a common electrode anda discrete electrode are connected to one of plural display cellsarranged in a matrix form, the method comprising the steps of: (a)supplying said common electrode with a reset pulse opposite in polarityto a display pulse, the reset pulse for inversion of charges stored onsaid common electrode; (b) supplying said common electrode with a firstsingle-step pulse of the same polarity as said display pulse; (c)applying said display pulse to the common electrode; and (d) applying acontrol voltage to said discrete electrode to thereby control a gaseousdischarge in said one of plural display cells.
 2. The display paneldriving method according to claim 1, wherein said step (b) is performedtwice in succession.
 3. The display panel driving method according toclaim 1, wherein the duration of said reset pulse is equal to or smallerthan 5 μs.
 4. The display panel driving method according to claim 1,wherein step (b) further comprises supplying a second single-step pulse,of the same polarity as said display pulse, to the common electrodewithin 1 μs after the rise of first single-step pulse.
 5. A method fordriving a display panel, in which a common electrode and a discreteelectrode are connected to one of plural display cells arranged in amatrix form, the method comprising the steps of: applying a displaypulse to the common electrode; applying a control voltage to thediscrete electrode to thereby control a gaseous discharge in said one ofplural display cells; and transferring data, for controlling a period ofthe gaseous discharge in said one of plural display cells, to a drivecircuit of the discrete electrode substantially when no voltage isapplied to the common electrode.
 6. The display panel driving methodaccording to claim 5, wherein a voltage of the display pulse rises intwo steps, and the application of the control voltage to the discreteelectrode is started following the rise of a first-step voltage andpreceding the rise of a second-step voltage.
 7. A method for driving adisplay panel, in which a common electrode and a discrete electrode areconnected to one of plural display cells arranged in a matrix form, themethod comprising the steps of: (a) applying an initialization sequencevoltage to the common electrode; (b) applying a stabilization sequencein which at least one display pulse is applied to the common electrodeto perform a stabilizing gaseous discharge of each of said pluraldisplay cells; and (c) controlling a period of the gaseous discharge insaid one of plural display cells by controlling a period in which toapply said display pulse to the common electrode and in which to apply adischarge suppression pulse to the discrete electrode.
 8. The displaypanel driving method according to claim 7, wherein a stabilizationperiod in which not to apply voltages to both of the common electrodeand the discrete electrode of said each of said plural display cells isset between at least one of the steps (a) and (b) and the steps (b) and(c).
 9. A method for driving a display panel, in which a commonelectrode and a discrete electrode are connected to one of pluraldisplay cells arranged in a matrix form, the method comprising the stepsof: (a) removing charges that trigger an unintended discharge of the oneof plural display cells during a stabilization period in which voltagesare not applied to either the common electrode or the discreteelectrode; (b) applying a display pulse to the common electrode toperform a gaseous discharge of said display cell; and (c) controlling aperiod of the gaseous discharge in said one of plural display cells bycontrolling a period in which to apply said display pulse to the commonelectrode and in which to apply a discharge suppression pulse to thediscrete electrode.
 10. The display panel driving method according toclaim 1, wherein a ratio of a first duration, from a termination of saiddisplay pulse to a start of said reset pulse, to a second duration, ofsaid reset pulse, is approximately 3:1.
 11. The display panel drivingmethod according to claim 4, wherein in step (b), the second single-steppulse falls within 1 μs after a falling of the first single-step pulse.